The invention relates to the field of manufacturing semiconductors in the form of integrated circuits.
It relates to photolithographic techniques and to techniques for obtaining planeness as used in the manufacture of integrated circuits. More particularly, the present invention relates to techniques which make it possible to obtain planeness of substrates in advanced lithography, i.e. to mechanical and chemical polishing and planarization.
In the steps of manufacturing an integrated circuit, layers of semiconductive, insulating, or metallic materials need to be deposited and then to be subjected to lithography and etching. These layers can be of various topographies, i.e. they can be plane or in relief.
In conventional manner, lithography takes place by depositing a layer of photosensitive resin on a layer that is to be subjected to lithography, and then sensitizing certain zones only of the resin which are then developed in a developer that is adapted to the chemical nature of the resin, thereby revealing specific zones of the layer for lithography.
The lithography step, like the steps of depositing the various materials, takes place with much better results when the underlying surface is plane. However, during manufacture of integrated circuits with successive operations of deposition and etching being performed, the uneveness of substrate topography increases to such an extent as to cause the implementation of certain steps to become critical.
That is why xe2x80x9cplanarizationxe2x80x9d techniques are used to make the topography planar from the beginning of integrated circuit manufacture.
Those techniques can comprise so-called xe2x80x9cetch-backxe2x80x9d planarization which consists in depositing a layer of resin which flattens the relief, with planeness being transferred to the substrate by plasma etching or by mechanical and chemical polishing which consists in abrading a thick layer of insulating or conductive material deposited on the substrate.
Obtaining planeness is vital during the initial steps of manufacturing integrated circuits and in particular when manufacturing transistor-isolating zones.
At present, isolating zones are generally made plane by mechanical and chemical polishing.
Nevertheless, that technique encounters certain limitations associated with the ever decreasing dimensions used for manufacturing circuits of ever increasing density. One method of improving the performance of mechanical and chemical polishing is to use a pre-planarization technique by back-masking and etching.
Those known planarization techniques are described below.
Over the last few years, the mechanical and chemical polishing technique has generally replaced other planarization techniques because of its better long distance uniformity and its better rate of throughput.
The principle of the mechanical and chemical polishing technique is to abrade layers (generally of silica and more recently of copper) by mechanical rubbing with an abrasive cloth (using rotary motion or movement in translation) under a certain pressure and in the presence of a solution that is chemically aggressive relative to the layer to be abraded. The combined chemical and mechanical abrasion enables abrasion speed to be high and enables the anisotropic nature of the attack to be adjusted over the entire surface of the wafer with good overall uniformity (chemical attack is more isotropic, while mechanical attack is more directional).
Nevertheless, although uniformity is good at very long range, the mechanical and chemical polishing technique, like the other planarization techniques, remains sensitive to topographical density. Sensitivity to topographic density is of the order of 100 microns for techniques making use of planarization obtained by depositing a layer of resin and it is of millimeter order for the mechanical and chemical polishing technique. As a consequence, in chips where there are very dense zones that are a few millimeters wide separated by zones that are less dense, the so-called xe2x80x9cdishingxe2x80x9d effect is observed which is manifested by the less dense zones (or those which offer little resistance to abrasion) becoming dished or by the denser zones (which withstand abrasion) bulging, as shown in accompanying FIG. 1.
In FIG. 1, reference 10 designates a semiconductive substrate having zones 12 of lower density and zones 14 of greater density, and 30 represents a cloth used for mechanical polishing, in this case by rotating relative to the substrate 10 about an axis Oxe2x80x94O perpendicular to the mean plane of the substrate 10.
Because of this density-related effect, the mechanical-and chemical polishing technique is restricted to planarizing structures with dimensions greater than 0.3 xcexcm.
For smaller technologies, the mechanical and chemical polishing technique is preceded by pre-planarization by back-masking and etching all of the positive topographical elements as shown in FIGS. 2a to 2c. 
More precisely, in these FIGS. 2a, 2b, and 2c, 10 designates a substrate having various layers of semiconductive, insulating, or metallic material, depending on the desired function, with a top layer 16, e.g. an oxide layer, that initially presents markedly uneven topography, as can be seen in FIG. 2a, i.e. it has portions in relief.
As shown in FIG. 2a, a layer of photosensitive resin 20 is deposited on the layer 16.
Then a mask 22 is superposed on said photosensitive layer 20. The mask 22 has openings 24 of a shape that matches the projections in relief of the layer 16 and that are superimposed respectively over them.
A flux of radiation 26 to which the resin 20 is sensitive, e.g. ultraviolet radiation, is applied to the resin layer through the mask 22.
Then the layer of resin 20 is developed.
This gives rise, as shown in FIG. 2b, to elements 21 of the resin layer 20 remaining on the top layer 16 of the substrate between the marked portions in relief of said layer 16.
Mechanical polishing is then performed using a cloth 30, as shown in FIG. 2c. 
That known technique as shown in FIGS. 2a, 2b, and 2c is generally referred to as xe2x80x9cpre-planarization by back-masking and direct etching of lateral isolating structures by shallow trenches prior to mechanical and chemical polishingxe2x80x9d, with such Shallow Trench Isolating structures also being referred to by the initials STI.
The prior techniques described above are restricted to 0.3 micron technologies when the mechanical and chemical polishing technique shown in FIG. 1 is used on its own.
They are limited to 0.25 micron technologies when used in conjunction with the technique of pre-planarization by back-masking and etching of the positive topographical element as shown in FIG. 2.
The latter technique is limited by problems of potential misalignment between the mask 22 and the topography of the underlying semiconductor device, which problems are inherent to photolithography. The misalignment can be of the order of 0.1 xcexcm, and it can lead to undesirable over-etching of insulating zones when the mask 22 is offset.
For technologies smaller than or equal to 0.18 microns, another technique is therefore required.
A technique of pre-planarization by depositing two successive layers of resin is sometimes used. That technique is known as two-layer planarization or TLP. A description can be found in document [1]. That technique is shown diagrammatically in FIGS. 3a to 3d. FIG. 3a shows a substrate 10 having various layers of semiconductive, insulating, or metallic material, including a top layer 16 that initially presents markedly uneven topography (see FIG. 3a).
A first layer of photosensitive resin 20 is deposited and lithographed with a special back-mask 22 having its openings 24 of reduced size (see FIG. 3a) and consequently giving rise to patterns of reduced size in the resulting resin 21 that is used to mask the isolating zones on the substrate 10 (see FIG. 3b).
This means that centering of the mask is insensitive to misalignment and allows the resin to flow thermally into the isolating recesses (see FIG. 3c). Heat treatment also serves to cure the first layer 20, thereby making it insoluble and enabling a second layer 28 to be deposited.
The second layer 28 planarizes the residual undulations and enables an almost plane surface to be obtained over the entire surface area, as shown in FIG. 3c. 
After both layers of resin have been deposited, the planeness of the surface is transferred to the substrate by plasma etching as represented in FIGS. 3c and 3d under conditions such that the resin 20, 28, and the underlying oxide layer 16 are all etched at the same speed. Etching is stopped 100 nanometers above the active zone layer, e.g. a nitride layer, and the wafers are transferred to a mechanical and chemical polishing station where planarization is continued and stopped in the nitride layer so as to obtain a plane structure with isolation zones embedded in the silicon.
Nevertheless, that technique is still sensitive to topographical density since the zones of the substrate having very small patterns are excluded because of the reduction in the size of the patterns in the resin (see FIG. 3b) due to the reduction in the size of the openings 24 in the mask 22. If these zones are large, they give rise to a phenomenon similar to the dishing effect encountered in pure mechanical and chemical polishing, as shown in FIGS. 4a to 4e. 
In FIGS. 4a to 4e: 
FIG. 4a shows the substrate 10 having the layer in relief 16 prior to the planarization process;
FIG. 4b shows the structure after deposition and photolithography of the first layer 20;
FIG. 4c shows the structure after the second layer 28 has been deposited and annealed;
FIG. 4d shows the structure after plasma planarization (transfer of the plane profile); and
FIG. 4e shows the structure after mechanical and chemical polishing.
In FIG. 4e, there can be seen a dimensional difference between dense zones (smaller thickness) and other zones, as a result in particular of the absence of any traces of the first layer 20 prior to deposition of the second layer 28 (and thus prior to plasma etching and mechanical and chemical polishing) over the dense zones.
In this context, the object of the present invention is to propose novel means enabling the planeness of semiconductor devices to be improved during the process of manufacturing them.
The present invention achieves this object by a method of correcting topographical effects on a micro-electronic substrate, the method comprising the steps consisting in:
i) depositing a first layer of resin on the structure to be planarized that has topography in relief surrounded by isolation zones;
ii) subjecting said resin layer in its zones superposed over underlying zones of low topographical density to photolithography by means of a mask imposing resin patterns of a size smaller than the underlying isolation zones to be masked;
iii) subjecting the resin layer in its zones superposed on underlying zones of high topographical density to photolithography through a mask possessing a standard mesh without any one-to-one coincidence with the underlying topography wherein said step iii) of photolithography through a mask possessing a standard mesh consists in adjusting the insolation to obtain optimum filling of large topographically dense zones;
iv) subjecting the first layer of resin as photolithographed in this way to thermal flow so that the resulting zones of the first layer of resin cover the isolation zones;
v) depositing a second layer of resin;
vi) performing plasma etching; and then vii) performing mechanical and chemical polishing.